Synchronous dynamic random-access memory (SDRAM) is one class of memory used in mobile communication and computing devices, such as smart phones and tablet computers. In some embodiments, double data rate SDRAM (DDR SDRAM or DDR) refers to a type of memory and an associated interface for communicating with the memory. Furthermore, low power DDR (LPDDR or simply LP), sometimes referred to as mobile DDR, is a class of DDR designed to reduce power consumption, with mobile devices being a target application. There are several versions of LPDDR corresponding to various data speeds and power requirements. For example, LPDDR3 (also sometimes denoted as LP3) and LPDDR4 (also sometimes denoted as LP4) are two recent versions of LPDDR. LPDDR4 is designed to communicate at a higher speed and consume less power than LPDDR3 at the expense of increased cost and/or complexity.
A trend in modern mobile devices, such as smartphones, is to focus memory designs on ever greater memory transfer rate while at the same time conserving power. A system on chip (SoC) is often used in mobile devices to conserve power and/or minimize space requirements. A SoC refers to multiple functional blocks, such as modems and application processor cores, embedded on a single substrate, allowing mobile devices to execute complex and power intensive applications. The single substrate is sometimes referred to as a die, so multiple functional blocks are commonly implemented on a single die.
In some instances, a package-on-package (PoP) can refer to a packaging configuration in which two or more packages are stacked on top of each other with an interface to pass signals between them. The Joint Device Engineering Council (JEDEC) has standardized one or more PoP footprints for interfacing with an LPDDR3 SDRAM memory. There is at least one proposal in JEDEC for a PoP footprint for interfacing with an LPDDR4 SDRAM memory. Differences in LPDDR3 and LPDDR4 result in the corresponding footprints being significantly different.
Mobile device applications are demanding more and faster memory, so the tendency is to focus SoC, and corresponding die, designs on optimizing routing and packaging for faster memory, such as LPDDR4. However, it may be desirable in price-sensitive markets, such as markets that focus on low or mid-tier smartphones, to offer the flexibility to vendors to tradeoff price and performance to offer mobile devices at different price points. One of the options may be to offer LPDDR3, as opposed to LPDDR4, as a lower-cost memory alternative. However, once an SoC die is optimized for LPDDR4 packaging, it may be overly costly to retrofit routing and packaging for LPDDR3. Thus, there is a need for SoC dies that flexibly accommodate different memory architectures.